According to conventional practice, and due largely to the historical dominance of cathode ray tube displays, video signals are formatted for broadcast or communication to display devices by a process of serialization. For convenience, such displays will be referred to herein as serial displays. Each successive two-dimensional picture or frame in a serial display is scanned in a repeating zigzag pattern along horizontal lines and vertically down the picture in successive lines. At each point in time, the color and intensity for a particular position on the display is defined in the video signal. This signal is digitized, and is also typical of direct digital sources such as MPEG decoders and computer display subsystems. This is to say that conventional temporal ordering of the two-dimensional picture data is preserved when an analog signal is digitalized, and is also typical of direct digital sources such as MPEG decoders and computer display subsystems. This is to say that conventional video ordering (and display) is such that the bits making up a pixel's data word are communicated together in time; pixels are communicated one after another to form a line; the line sequence of successive lines defines frames; a full video sequence is defined frame by frame. Thus, the image data is received at the scan rate of such a conventional display device. Because of this there is no need to store the image data in an ordinary television or similar display device.
So-called digital displays are now well known in the art. When displaying an image using a digital display device, a data bit defines the state of each picture element (pixel). Thus, each pixel is either `on` or `off` according to the binary state of the data bit. To form a more variable image it is desirable to provide selectable grayscale using pulse width modulation (PWM) and such increased variability can be used to provide more information or more realism in an image. For example, consider a display where an `on` pixel is white and an `off` pixel is black. To achieve an in-between state, e.g. gray, the pixel can be toggled equally between `on` and `off`. If the pixel display duration is sufficiently short, the viewer's eye/brain system automatically integrates this toggled pixel to perceive a gray image rather than black and white. To achieve a lighter or darker gray, the duty cycle for toggling the pixel can be adjusted so the pixel is on more or less of the time according to the state of a multiple corresponding bits of a signal word. In other words the width of the `on` pulse is adjusted (modulated) in relation to the width of the `off` pulse to alter the degree of brightness/darkness of the pixel.
The techniques for using PWM to generate grayscale are directly applicable to technologies using PWM to generate color in display technologies. To avoid obscuring the present invention in unnecessary and extraneous detail, some portions of the prior art and the invention will be described relative to the formation of a black and white grayscale display only. It will be apparent to one of ordinary skill in the art that these techniques can be directly applied to forming a color display combination using primary colors. It will be understood that color is also contemplated within the teachings of the invention.
Weighted PWM schemes modulate an output by utilizing a display duration divided into smaller segments of varying durations. A bit's weight is governed by the time a data value is present on a pixel, that is, the time between being written and later overwritten. Conventional schemes use a binary radix number coding and weighing where each bit in the pixel's signal word has half the weight of its predecessor and the corresponding segments duration is scaled in the same manner. The modulated signals activated during all, some or none of the segments in the frame to develop a signal representing a particular parameter. This method and apparatus can be used in a display for selecting among varying levels of gray. Conventionally, a binary weighted grayscale can select among 2.sup.n levels of gray where n is the number of bits in the binary weighting.
One type of digital displays are known as silicon light modulators. One example of a silicon light modulator is taught in U.S. Pat. No. 5,311,360 issued May 10, 1994 to Bloom, et al. which is incorporated herein by reference. Another silicon light modulator is taught by European Patent application serial number EP-94100308, and applied for by Texas Instruments. Unlike the serial displays of the prior art, this type of digital display does not update the display one pixel at a time. In one type of display taught by Texas Instruments, all the pixels of the array are simultaneously updated. For a present day high resolution display having 1024.times.1280 pixels, and consequently 1,310,720 pixels need to be updated at a time.
For this reason among others, certain silicon light modulator arrays (in the form of chips or components) are updated in groups of pixels rather than all pixels of the arrays at once, thus alleviating much of the interconnection and bandwidth problems associated with transferring a million or more data bits at once. For example, see U.S. patent application Ser. No. 08/473,750 filed Jun. 7, 1995 and also U.S. patent application Ser. No. 08/635,479, filed Apr. 22, 1996, both incorporated herein by reference. An update is the event by which such a group of data is transferred to the light modulator and is displayed. The ordering of update events in time--commonly referred to as `addressing`--generates the desired PWM effect such that an update punctuates a previous update's time period by overwriting old data and initiating a new time period. In U.S. Pat. No. 5,311,360 the silicon light modulator comprises a Grating Light Valve (GLV). In that reference for instance, a group comprises a complete horizontal line or "row" of pixels and a row is updated in parallel.
As discussed above, in a PWM video display system the bits in the digital data word defining the gray level of a particular pixel arrive in a serial data stream, pixel by pixel. However, in a silicon light modulator, the data updates occur at various points in time dispersed through the frame period. Therefore, when displaying a conventional video source on a digital PWM display, buffer memories are required to interface between the incoming video and the silicon light modulator. An incoming video signal is generally not PWM, but rather is digitally coded, generally binary. The video display signal is PWM. A typical relationship between incoming video data timing and displayed data timing is illustrated in FIG. 1 for a 4-bit grayscale. Note that the most significant bit (MSB) of data from line 0 cannot be used in a display update until data from line 1023 has been received; line 0 MSB and all intermediate data values have to be stored in the mean time.
Interfacing between the incoming video and the silicon light modulator, according to conventional practice, a double-buffered frame store is used. Here, one memory bank is written with data from an incoming video frame, while data from the preceding frame is simultaneously read from the second bank. At the end of the frame time, the banks' functions are interchanged: the bank previously written is now read out, while the bank previously read is now overwritten with new frame date. Such a system must have sufficient memory capacity to hold two complete frames of video information. In the high resolution 1024.times.1280 and consequently for the system discussed above, information for two times 1,310,720 pixels (2,621,440 pixels) are stored. In an eight bit grayscale PWM system, these frame buffers must contain data storage for 20,971,520 bits. Color systems conventionally have three times that requirement for data storage. Additionally, the memory system requires a sustained bandwidth of 700 megabytes/second or above counting both read and write accesses in a color 1024.times.1280 color system. An implementation according to these requirements will be very expensive using commercially available RAM components. Previous disclosures have described optimizations for silicon light modulator device simplification, peak bandwidth reductions for buffer memory and silicon light modulator interfacing, but have assumed or described double buffered frame stores as part of the drive system.
Additionally, throughout the duration of the frame period, a complete frame's data is available for forming a corresponding PWM display addressing scheme. In other words, once all the data for a single frame is stored, the like-weighted bits for a group, such as a row, are collected and simultaneously displayed in that row. Thus, not only must such a system have the significant memory storage capability described above, but that memory must have a combined read-write bandwidth capability to supporting a least twice the incoming video data rate. In such systems this requires a sustained bandwidth of 750 megabytes/second. or more (20 costly memory chips in current technology). Previous disclosures have described optimization for silicon light modulator device simplification, peak bandwidth reduction for buffer memory and silicon light modulator interfacing, but have assumed or described double buffered frame stores as part of the drive system.
What is needed is a digital display system providing PWM grayscale and/or color which does not require the support of a fully double-buffered, high-speed frame store memory in order to interface with conventional video sources.